Our Story

Secure Hardware Design was created by Mengjia Yan with the mission to teach the next generation of computer architects how to design great processors.

Here’s a look back at how we’ve been thinking, playing, and doing for the past few years.

Fall 2020

We launched SHD as a seminar course during the pandemic.

Lecture	Six lectures focused on side channels and Trusted Execution Environments (TEEs).
Lab	Students completed a cache attack lab and an open-ended final project. One of the projects led to the publication of the Bigger Fish paper.
Paper Discussion	The first offering of the course focused on teaching students read research papers, and thus was heavy on paper discussions.

Driven by the great passion of Joseph Ravichandran, significant updates have been implemented in this iteration, making it a popular and lab-rich course. The status of the course was captured in a SigArch Blog post.

Lecture	Eleven lectures covering a wider range of topics including side channel attacks, physical attacks, Rowhammer, and CPU fuzzing.
Recitation	We introduced hands-on hacking recitations this year, running four capture-the-flag (CTF) sessions. We gave out several FTDI UART adapters and microcontrollers as prizes, and ran two pizza parties.
Lab	We had a full-fledge hardware security lab suits, consisting of five exciting lab assignments on hacking real processors, including the new kernel Spectre attack lab, website fingerprinting lab, Rowhammer lab, and ASLR bypass lab. One of these labs inspired the discovery of the EntryBleed attack (HASP’23 Best Paper Award).
Paper Discussion	The discussion sessions were streamlined with each one strategically scheduled after the corresponding lecture to reinforce the foundational knowledge covered. For a detailed schedule, please refer to the calendar.

Spring 2023

We stablized course content and polished the lab organziations. Meanwhile, we started receiving multiple requests around the world to use our course materials.

Lecture	We introduced multiple in-class demos.
Recitation	Two new recitation sessions are introduced: one on RISCV system programming and the other on formal evaluation of Register Transfer Level (RTL) code.
Lab	We introduced a new capstone design project where students design end-to-end fuzzers on a custom RISCV chip for detecting hidden instructions.
Paper Discussion	We further reduced the number of paper discussion sessions to emphasize its supplementary role.

Spring 2024

SHD is listed as a TQE course at MIT starting from this offering.

Lecture	We added a new lecture on formal verification for hardware security.
Lab	A new lab assignment was added to guide the students to use the Yosys-Rosette toolchain to detect hardware bugs. The difficulty level is ‘‘easy’’. The difficulty level of the Rowhammer lab is also reduced.

Spring 2025

We are constantly working diligently to make Secure Hardware Design better than ever. Here’s where we’re going with it for this year and beyond.

Lab	A new lab assignment will be added to guide the students to debug C code and test students’ basic C knowledge. Mid-checkpoints will be added to several labs with heavier workload to guide the students to plan ahead and start early. Furthermore, we will slightly increase the difficulty level of 50% of the labs.
Paper Discussion	The grading policy for paper discussions will be revised to emphasize and reward thorough preparation and the use of effective visualizations that enhance the class’s understanding.

Acknowledgements

This course stands as an outcome of the combined efforts of many passionate students.

Joseph crafted three of the six lab assignments that have challenged and intrigued our students, from the kernel Spectre attack lab to the ASLR bypassing lab and the ingenious hardware fuzzing lab. He also designed a lecture on physical attacks that featured three captivating in-person attack demonstrations. Moreover, Joseph created all the eye-catching flyers and advertisement materials.
Peter and Miguel designed the Rowhammer lab, challenging students to delve deep into the intricate world of hardware vulnerabilities.
Yuheng took the lead in designing the hardware formal verification recitation session. Building on that success, Yuheng is now expanding it into a full-fledged lab.
Jack designed the website fingerprinting lab. This lab serves as a delightful warm-up for the course, and it imparts a thought-provoking lesson about the challenges of uncovering the root causes of side channels within complex systems.
Our very first TA, Miles, added the CTF component to the cache lab.