Lecture Readings

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	Background Reviews and Related Books	Research Papers (mentioned in class)	Fun Readings and Videos
L01: Overview	6.191 [6.004] slides: L01 The Digital Abstraction L12 Memory Hierarchy L13 Caches L15 Pipelined Processors: Data and Control Hazards L16 Operating Systems L17 Virtual Memory 1 L18 Virtual Memory 2 L22 Modern Processor Architecture		USENIX ATC '21/OSDI '21 Joint Keynote Address-It's Time for Operating Systems to Rediscover Hardware
L02: Side Channel Overview		DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (Section I) A retrospective on the VAX VMM security kernel. 1991 (Section VI-E)	Side Channel Security Youtube Channel
L03: Deep Dive of Cache Side Channels		FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack Last-Level Cache Side-Channel Attacks are Practical Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World	EntryBleed: Breaking KASLR under KPTI with Prefetch
L04: Transient Execution Side Channels	6.5900 [6.823] L06 Complex Pipelining Scoreboarding (Recording) (covered in the lecture, but if want to get more details about out-of-order execution)	On the Spectre and Meltdown Processor Security Vulnerabilities Meltdown: Reading Kernel Memory from User Space Spectre Attacks: Exploiting Speculative Execution Speculative Load Hardening: A Spectre Variant #1 Mitigation Technique MDS: Microarchitectural Data Sampling
L05: Hardware-Software Contracts		Hardware-Software Contracts for Secure Speculation ARM. DIT, Data Independent Timing Intel. Data Operand Independent Timing Instruction Set Architecture (ISA) Guidance FaCT: A DSL for Timing-Sensitive Computation Secure, Precise, and Fast Floating-Point Operations on x86 Processors BearSSL. Constant-time Crypto
L06: Side-channel Mitigations		Complete Information Flow Tracking from the Gates Up New Attacks and Defense for Encrypted-Address Cache Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
L07: Hardware Security Module (HSM)	Intel SGX Explained (Section 3.1-3.3, 4.1, 4.4-4.5) Principles of Secure Processor Architecture Design* (Chaper 5 Hardware Root of Trust)	Building the IBM 4758 Secure Coprocessor. 2001 Apple Platform Security (Page 5-96)
L08: Physical Attacks (by Joseph Ravichandran)	6.191 [6.004] L01 The Digital Abstraction 6.191 [6.004] L06 Sequential Circuit The Hardware Hacking Handbook* (Chapter 1, 5, 8, 13; The whole book includes many practical tips on how to carry out physical attacks by yourself) Hacking the Xbox	Power Analysis Attacks: Revealing the Secrets of Smart Cards. 2007* Building a high-performance, programmable secure coprocessor. 1999 (Section 4)	Talk on Supply Chain Attacks & Verifiability
L09: Rowhammer Attacks	Memory systems: cache, DRAM, disk.* (Chapter 10 DRAM Memory System Organization)	Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors Flip Feng Shui: Hammering a Needle in the Software Stack CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86 The Story of Rowhammer - Keynote at Secure Hardware, Architectures, and Operating Systems Workshop (SeHAS) at the HiPEAC 2021 Conference	Exploiting the DRAM rowhammer bug to gain kernel privileges. Google Project Zero
L10: Rowhammer Mitigation + Reliability Solutions		Graphene: Strong yet Lightweight Row Hammer Protection REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking Revisiting Residue Codes for Modern Memories OpenTitan Website OpenTitan Github OpenTitan Talk in CHES 2022
L11: Hardware Support for Software Security	SoK: Eternal War in Memory	Smashing the Stack for Fun and Profit An Introduction to CHERI The Arm Morello Board Virtual memory primitives for user programs. 1991 Memory protection keys Qualcomm. Pointer Authentication on ARMv8.3 Design and Analysis of the New Software Security Instructions Armv8.5-A Memory Tagging Extension Intel. Control-flow Enforcement Technology Specification (Section 1-3) Control-flow integrity principles, implementations, and applications. 2005	xkcd. HeartBleed Explanation
L12: Fuzzing and Bug Finding		Computational aspects of the Pentium affair. 1995 Fuzzing Hardware Like Software SPECS: A Lightweight Runtime Mechanism for Protecting Software from Security-Critical Processor Bugs Bug Attacks HardFails: Insights into Software-Exploitable Hardware Bugs The Art, Science, and Engineering of Fuzzing: A Survey Branch History Injection: On the Effectiveness of Hardware Mitigations Against Cross-Privilege Spectre-v2 Attacks SiliFuzz: Fuzzing CPUs by proxy	Breaking the x86 Instruction Set. BlackHat Intel Pentium FPU glitch. 1994 A Stitch In Time Saves Nine: A Stitch In Time Saves Nine: A Case Of Multiple OS Vulnerability Riding the Fuzzing Hype Train (RAID'21 Keynote)
L13: Formal Verification for Hardware Security		The Complexity of Theorem-Proving Procedures. 1971 A Machine Program for Theorem-Proving. 1962 GRASP: A Search Algorithm for Propositional Satisfiability. 1999 End-to-End Verification of ARM Processors with ISA-Formal. 2016
L14: Trusted Execution Environment (TEE)	Intel SGX Explained (Section 5 SGX Programming Model)	SoK: Understanding Designs Choices and Pitfalls of Trusted Execution Environments AMD Secure Encrypted Virtualization (SEV) Protecting VM Register State With SEV-ES AMD SEV-SNP Keystone: An Open Framework for Architecting Trusted Execution Environments RISC-V Privileged Instructions (Section 3.6) Arm Confidential Compute Architecture (Arm Website) Intel Trust Domain Extensions (TDX)